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motorola semiconductor technical data 34923 simplified application diagram this document contains informat ion on a product under development. motorola reserves the right to change or discontinue this product without notice. ? motorola, inc. 2003 order this document from analog marketing: mc34923/d rev 0, 05/2003 34923 preliminary information ordering information device temperature range (t a ) package mc34923dw/r2 -40 to 125c 24 soicw full-bridge pwm motor driver designed with motorola?s advanced smartmos, the 34923 is designed for pulse-width modulated (pwm) current cont rol of dc motors. it is capable of continuous output currents up to 2.0 a and operating voltages of up to 45 v. internal fixed off-time pwm current-cont rol timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. dir and pwm/enable input pins are provided for use in controlling the speed and direction of a dc motor with externally applied pwm-control signals. the pwm/enable input can be programmed via the serial port to pwm the bridge in fast or slow current decay. internal synchronous rectification control circuitry is provided to reduce power dissipation during pwm operation. internal circuit protection includes t hermal shutdown with hysteresis and crossover-current protection. a specia l power-up sequencing is not required. features ? 2.0 a, 45 v continuous output rating ? low r ds(on) outputs (270 m ? , typical) ? programmable mixed, fast, and slow current-decay modes ? serial interface controls chip functions ? synchronous rectification for low power dissipation ? internal undervoltage lockout thermal shutdown circuitry ? crossover-current protection full-bridge pwm motor driver dw suffix 24-lead soicw case 751e-04 34923 5.0 v 5.0 v serial port clock data strobe pwmmode dir pwm/enable osc mcu dcma dcmb motor dc gnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 2 figure 1. 34923 simplified block diagram bandgap v dd thermal shutdown undervoltage and fault detect pwmmode dir pwm/enable control logic direction enable sync. rect.control internal pwm mode external pwm mode cp1 cp2 charge pump v b v bb bandgap regulator v reg gate drive dcma dcmb fixed-off blank decay programmable pwm timer osc data strobe span sense c s r s reference buffer and divider load current sense current zero current detect sleep mode serial port v ref clock v dd reference 5.0 v 45 v motor osc (160 khz) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 3 . pin function description pin pin name formal name definition 1v b boost voltage boost voltage storage node. 2 cp2 switching capacitor 2 charge pump capacitor connection 2. 3 cp1 switching capacitor 1 charge pump capacitor connection 1. 4 dir direction logic-level input for direction control. 5 osc oscillator logic- level oscillator (square wave) input. 6, 7, 18, 19 gnd ground ground. 8v dd logic voltage low voltage (typically 5.0 v) logic supply. 9 pwm/enable h-bridge enable logic-level i nput for enabling the h-bridge driver. 10 data serial data logic-level input for serial interface. 11 clock serial data clock logic-level input for serial port (data is entered on rising edge). 12 strobe serial data latch strobe logic-level i nput for serial port (active on rising edge). 13 v ref current limit reference voltage load current reference input voltage. 14 pwmmode pwm mode control logic-level input for pw m mode control when in internal pwm mode. 15, 22 nc no connect no inter nal connection to this pin. 16 dcma h-bridge output a one of two bridge outputs to the motor. 17 sense current sense sense resistor. 20 v bb h-bridge voltage supply high-current (20 v to 45 v) load supply. 21 dcmb h-bridge output b one of two bridge outputs to the motor. 23 span current limit reference range logic-level input for v ref range control. 24 v reg bandgap voltage bandgap decoupling capacitor. 5 6 7 8 9 10 11 12 2 3 4 24 20 19 18 17 16 15 13 23 22 21 14 1 v reg v bb gnd gnd sense dcma nc pwmmode v ref span nc dcmb v b osc gnd gnd v dd pwm/enable data strobe cp2 cp1 dir clock f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 4 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit load supply voltage v bb 48 v logic supply voltage v dd 7.0 v input voltage v in -0.3 to v dd + 0.3 v sense voltage v s 0.5 v reference voltage v ref 2.7 v output current (note 1) i out 2.0 a storage temperature t s -55 to 150 c ambient temperature t a -20 to 85 c operating junction temperature t j -40 to 150 c power dissipation (t a = 25c) (note 2) p d 1.6 (note 3) w esd voltage human body model (note 4) machine model (note 5) v esd1 v esd2 2000 200 v lead soldering temperature (note 6) t solder 260 c thermal resistance junction-to-ambient (note 2) r ja 56 c/w notes 1. output current rating may be limited by duty cycle, ambient temperature, and heatsink ing. under any set of conditions, do not exceed the specified current rating or a junction temperature of 150c. 2. maximum power dissipation at indicated ambient temperature in free air with no heatsink used. 3. per semi g42-88 specification. 4. esd1 testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ? ). 5. esd2 testing is performed in ac cordance with the machine model (c zap = 200 pf, r zap = 0 ? ). 6. lead soldering temperature limit is for 10 seconds maximum durat ion. not designed for immersi on soldering. exceeding these li mits may cause malfunction or permanent damage to the device. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 5 static electrical characteristics characteristics noted under conditions t a = 25 c, v bb = 45 v, v dd = 5.0 v, v sense = 0.5 v, and f pwm < 50 khz unless otherwise noted. characteristic symbol min typ max unit output drivers load supply voltage range operating during sleep mode v bb 20 0 ? ? 45 45 v output leakage current v out = v bb v out = 0 v i dss ? ? <1.0 <-1.0 20 -20 a output on resistance source driver, i out = -2.0 a @ 25c source driver, i out = -2.0 a @ 150c sink driver, i out = 2.0 a @ 25c sink driver, i out = 2.0 a @ 150c r ds(on) ? ? ? ? 300 ? 300 ? 450 700 450 700 m ? body diode forward voltage source diode, i f = -2.0 a sink diode, i f = 2.0 a v f ? ? 1.2 1.2 1.6 1.6 v load supply current f pwm < 50 khz charge pump on, outputs disabled sleep mode i bb ? ? ? 4.0 2.0 ? 7.0 5.0 20 ma ma a control logic logic supply voltage range (operating) v dd 4.5 5.0 5.5 v logic input voltage v in(1) v in(0) 2.0 ? ? ? ? 0.8 v input current all logic inputs except pwm/enable v in = 2.0 v v in = 0.8 v pwm/enable only v in = 2.0 v v in = 0.8 v i in(1) i in(0) i in(1) i in(0) ? ? ? ? <1.0 <-2.0 40 16 20 -20 100 40 a input hysteresis all digital inputs except osc osc (operating) ? v in(logic) ? v in(osc) 50 200 ? ? 100 400 mv reference input voltage range (operating) v ref 0?2.6v reference input current v ref = 2.5 v i ref ??0.5 a input offset voltage comparator v ref = 0 v buffer v io ? ? 0 0 5.0 15 mv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 6 control logic (continued) reference divider ratio bit d14 = high bit d14 = low ? 9.9 4.95 10 5.0 10.2 5.05 ? thermal shutdown temperature t j ? 165 ? c thermal shutdown hysteresis ? t j ?15?c undervoltage lockout enable threshold increasing v dd uvlo 3.90 4.2 4.45 v undervoltage lockout hysteresis ? uvlo 0.05 0.10 ? v logic supply current f pmw < 50 khz sleep mode, inputs <0.5 v i dd ? ? 6.0 ? 10 2.0 ma static electrical charac teristics (continued) characteristics noted under conditions t a = 25 c, v bb = 45 v, v dd = 5.0 v, v sense = 0.5 v, and f pwm < 50 khz unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 7 dynamic electrical characteristics characteristics noted under conditions t a = 25 c, v bb = 45 v, v dd = 5.0 v, v sense = 0.5 v, and f pwm < 50 khz unless otherwise noted. characteristic symbol min typ max unit control logic osc input frequency (operating) f osc 2.9?6.1mhz osc input duty cycle (operating) dc osc 40 ? 60 % propagation delay times pwm change to source on pwm change to source off pwm change to sink on pwm change to sink off direction change to sink on direction change to sink off direction change to source on direction change to source off t pd ? ? ? ? ? ? ? ? 600 100 600 100 600 100 600 100 ? ? ? ? ? ? ? ? ns f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 8 timing diagram figure 2. serial port write timing cde fg strobe a b d19 d18 d0 clock data legend id description value (ns) id description value (ns) a data setup time 15 e clock low pulse width 50 b data hold time 10 f setup clock rising edge-to-strobe 50 c setup strobe-to-clock rising edge 50 g strobe pulse width 50 d clock high pulse width 50 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 9 system/application information introduction the 34923 is designed for pulse-width modulated (pwm) current control of dc motors. it is capable of continuous output currents up to 2.0 a and operatin g voltages of up to 45 v. internal fixed off-time pwm current-control timing circuitry can be programmed via a serial interf ace to operate in slow, fast, and mixed current decay modes. dir and pwm/enable input pins are provided for use in controlling the speed and direction of a dc motor with externally applied pwm-control signals. the pwm/enable input can be programmed via the serial port to pwm the bridge in fast or slow current decay. internal synchronous rectification control circuitry is provided to reduce power dissipation during pwm operation. internal circuit protection in cludes thermal shutdown with hysteresis and crossover-current protection. special power-up sequencing is not required. functional pin description v b this pin provides a node for charge storage at the boost voltage. internal circuitry will draw v b current from this node, and the charge pump will deliver charge to this node. cp1 and cp2 these pins are the connections to the switching capacitor in the charge pump. these pins swing between ground and v b , drawing charge from v bb and delivering it to the v b node. dir this is the direction input for the h-bridge driver. pwm/enable this pin is the enable input for the h-bridge driver. when asserted this will bring the h-bridge out of tri-state mode so that it can drive a load. pwmmode this logic input controls the h-bridge output mode when the pwm is deasserted. the h-bridge can have an active or passive output state when the pwm input is deasserted. osc this logic input is the clock for the on-board decay time generator used only when in internal pwm mode. the decay time can be slow or mixed fast and slow. v dd this is the power supply input for the internal logic and several other functions. data this logic input is the serial data used by the serial interface. clock this logic input is the clock for the serial interface. data is shifted in synchronously with this clock. strobe this logic input is used to latch data from the serial interface into the internal logic. v ref this input provides a referenc e voltage for t he current limit comparator threshold. dcma and dcmb these are the high-current, high-v oltage drive signals for the motor. v bb this is the motor drive voltage input. the h-bridge will deliver this voltage to the motor. span this logic-level input controls the current limit comparator threshold that is generated from v ref . v reg this output is a decoupling node for the internal bandgap reference voltage generator. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 10 functional description serial interface the 34923 is controlled via a 3-wire (clock, data, strobe) serial port. the programmable functions allow maximum flexibility in configuring the pwm to the motor drive requirements. the serial data is clocked in starting with bit d19. d0?d1, blank time the current-sense comparator is blanked when any output driver is switched on in accordance with the table below. f osc is the oscillator input frequency. d2?d6, fixed off-time a five-bit word sets the fixed off-time for internal pwm current control. the off time is defined as follows: t off = (8[1 + n] /f osc ) - 1/f osc where n = 0 to 31. for example, with an oscillator frequency of 4.0 mhz, the off- time is adjusted from 1.75 s to 63.75 s in increments of 2.0 s. d7?d10, fast decay time a four-bit word sets the fast de cay portion of the fixed off-time for the internal pwm control circuitry. this will only have impact if the mixed current decay mode is selected (via bit d17 and the pwmmode input pin). for t fd > t off , the device will effectively operate in the fast decay mode . the fast decay portion is defined as follows: t fd = (8[1 + n]/f osc ) - 1/f osc where n = 0 to 15. for example, with an oscillator frequency of 4.0 mhz, the fast decay time is adjusted from 1.75 s to 31.75 s in increments of 2.0 s. d11?d12, synchronous rectification control the active mode prevents reversal of load current by turning off synchronous rectification when a zero current level is detected. the passive mode will allow reversal of current but will turn off the synchronous rectifier circuit if the load current inversion ramps up to the current limit set by v ref /r s . d13, external pwm decay mode bit d13 determines the current decay mode when using pwm/enable chopping for external pwm current control. bit function d0 blank time lsb d1 blank time msb d2 fixed off-time lsb d3 fixed off-time bit 1 d4 fixed off-time bit 2 d5 fixed off-time bit 3 d6 fixed off-time msb d7 fast decay time lsb d8 fast decay time bit 1 d9 fast decay time bit 2 d10 fast decay time msb d11 synchronous rectification mode d12 synchronous rectification enable d13 external pwm decay mode d14 enable logic d15 direction logic d16 divisor span select d17 internal pwm mode d18 test mode d19 sleep mode d0 d1 blank time 0 0 4/f osc 1 0 6/f osc 0 1 12/f osc 1 1 24/f osc d11 d12 synchronous rect. control 0 0 disabled 0 1 active 1 0 disabled 1 1 passive d13 current decay mode 0 fast 1 slow f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 11 d14, enable logic bit d14, in conjunction with the pwm/enable pin, determines if the output drivers are in the chopped (off) or on state. d15, direction logic bit d15, in conjunction with the dir pin, determines if the device is operating in the forward or reverse state. d16, divisor span select bit d16, in conjunction with th e span pin, determines if v ref is divided by 5 or 10. d17, internal pwm mode bit d17, in conjunction with the pwmmode pin, selects mixed or slow current decay. d18, test mode bit d18 low (default) operates the device in normal mode. d18 is only used for testing purposes. the user should never change this bit. d19, sleep mode bit d19 selects a sleep mode to minimize power consumption when not in use. this disables much of the internal circuitry, including the regulator and charge pump. on power-up the serial port is initialized to all zeros. bit d19 should be programmed high for 1.0 ms before attempting to enable any output driver. serial port write timing operations data is clocked into the shift register on the rising edge of the clock signal. normally strobe will be held high, only brought low to initiate a write cycle. refer to figure 2, serial port write timing , page 8, for the minimum timing requirements. v reg this internally generated voltag e is used to operate the sink- side outputs. the v reg pin should be decoupled with a 0.22 f capacitor to ground. v reg is internally monitored and, in the case of a fault condition, the outputs of the device are disabled. charge pump the charge pump is used to generate a gate supply voltage greater than v bb to drive the source-side gates. a 0.22 f ceramic capacitor should be connected between cp1 and cp2 for pumping purposes. a 0.22 f ceramic capacitor should be connected between v b and v bb to act as a reservoir to operate the high-side devices. the v b voltage is internally monitored and, in the case of a fault condition, the source outputs of the device are disabled. shutdown in the event of a fault (excessive junction temperature or low voltage on v b or v reg ), the outputs of the device are disabled until the fault condition is removed. at power-up, and in the event of low v dd , the undervoltage lockout circuit disables the drivers and resets the data in the serial port to all zeros. pwm timer function the pwm timer is programmable via the serial port (bits d2? d10) to provide off-time pwm signals to the control circuitry. in the mixed current-decay mode, the first portion of the off time operates in fast decay, until the fa st decay time count (serial bits d7?d10) is reached, followed by slow decay for the rest of the off-time period (bits d2?d6). if the fast decay time is set longer than the off time, the device effectively operates in fast decay mode. bit d17, in conjunction with pwmmode, selects mixed or slow decay. pwm/ enable d14 operating mode 0 0 chopped 1 1 1 0 on 0 1 state dir d15 dcma dcmb reverse 0 0 low high 1 1 forward 1 0 high low 0 1 divisor span d16 5 1 0 0 1 10 0 0 1 1 pwmmode d17 current decay mode 0 0 mixed 1 1 1 0 slow 0 1 d19 sleep mode 0 sleep 1 normal f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 12 pwm blank timer when a source driver turns on, a current spike occurs owing to the reverse recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. to prevent this current spike from erroneously resetting the source-enable latch, the sens e comparator is blanked. the blank timer runs after the off-time counter (see bits d2?d6) to provide the programmable blanking function. the blank timer is reset when pwm/enable is chopped or dir is changed. for external pwm control, a dir change or pwm/enable on will trigger the blanking function. synchronous rectification when a pwm off cycle is triggered, either by an pwm/ enable chop command or internal fixed off-time cycle, load current will recirculate accordin g to the decay mode selected by the control logic. the 34923 synchronous rectification feature will turn on the opposite pair of outputs during the current decay and effectively short out the body diodes with the low r ds(on) driver. this will reduce power dissipation significantly and can eliminate the need for external schottky diodes. synchronous rectification can be configured in active mode, passive mode, or disabled via the serial port (bits d11 and d12). the active or passive mode selection has no impact in slow- decay mode. with synchronous re ctification enabled, the slow- decay mode serves as an effective brake mode. current regulation load current is regulated by an internal fixed off-time pwm control circuit. when the output s of the h-bridge are turned on, the current increases in the motor winding until it reaches a trip value determined by the external sense resistor (r s ), the applied analog reference voltage (v ref ), the span logic level, and serial data bit d16: when span = d16, i trip =v ref /10r s when span d16, i trip =v ref /5r s at the trip point, the sense comparator resets the source- enable latch, turning off the sour ce driver. the load inductance then causes the current to recirculate for the serial-port- programmed fixed off-time per iod. the current path during recirculation is determined by th e configuration of slow/mixed current-decay mode (d17) and the synchronous rectification control bits (d11 and d12). internal pwm (current mode) pwm frequency the internal pwm opeating frequency is set by the sum of ?off time?, as determined by bits d2 through d6, ?blank time?, as determined by bits d0 and d1 , and the time constant of the motor. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 13 applications current sensing to minimize inaccuracies in sensing the i trip current level, which may be caused by ground trace ir drops, the sense resistor should have an independent ground return to the ground pin of the device. for low- value sense resistors, the ir drops in the pcb sense resistor?s traces can be significant and should be taken into account. the use of sockets should be avoided because they can introduce variation in r s owing to their contact resistance. the maximum value of r s is given as r s 0.5/i trip . braking the braking function is implem ented by driving the device in slow-decay mode via serial port bit d13, enabling synchronous rectification via bit d12, and chopping with the combination of d14 and the pwm/enable input pin. because it is possible to drive current in either direct ion through the drivers, this configuration effectively shor ts out the motor-generated back emf (bemf) as long as the pwm/enable chop mode is asserted. it is important to not e that the internal pwm current- control circuit will not limit the current when braking, because the current does not flow through the sense resistor. the maximum brake current can be approximated by v bemf /r l . care should be taken to ensure th at the maximum ratings of the device are not exceeded in worst-case braking situations of high-speed and high-inertial loads. thermal protection circuitry turns off all drivers when the junction temperature reaches 165c typically. it is in tended only to protect the device from failures owing to excessive junction temperatures and should not imply that output short circuits are permitted. thermal shutdown has a hysteres is of approximately 15c. layout the printed wiring board should use a heavy ground plane. for optimum electrical and thermal performance (see following note), the driver should be sol dered directly onto the board. the ground side of r s should have an individual path to the ground pins of the device. this path s hould be as short as is possible physically and should not have any other components connected to it. it is recommended that a 0.1 f capacitor be placed between sense and ground as close to the device as possible; the load supply pin, v bb , should be decoupled with an electrolytic capacitor (>47 f is recommended) placed as close to the device as is possible. note the thermal resistance and absolute maximum allowable package power dissipation specified in the maximum ratings table, page 4, is measured on typical two-sided pcb with minimal copper ground area. for the 34923, r ja can be reduced to 56c/w with 3.57-in 2 copper ground area, as shown in figure 3 . figure 3. package dissipation temperature derating allowable package power dissipation watts temperature (c) 50 100 150 125 5 4 3 2 1 0 75 25 r ja = 56c/w f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
34923 motorola analog integrated circuit device data 14 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. -a- -b- p 12x d 24x 12 13 24 1 m 0.010 (0.25) b m s a m 0.010 (0.25) b s t -t- g 22x seating plane k c r x 45 m f j dim min max min max inches millimeters a 15.25 15.54 0.601 0.612 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 dw suffix 24-lead soic wide body plastic package case 751e-04 issue e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 34923 15 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: japan: motorola japan ltd.; sps, technical information center motorola literature distribution 3-20-1 minami-azabu. minato-ku, tokyo 106-8573, japan p.o. box 5405, denver, colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 asia/pacific: motorola semiconductors h. k. ltd.; silicon harbour centre 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc34923/d information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2003 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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